1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to efficiently reducing lock time of a dual-path phase locked loop (PLL).
2. Description of the Relevant Art
A phase-locked loop, or phase lock loop, (PLL) is an electronic control system for relating a phase and a frequency of a generated output signal to a phase and a frequency of a received input signal. In general, a frequency of an alternating signal is derived from a phase of the alternating signal. Therefore, maintaining the output phase of the output signal in lock step with the input phase of the input signal results in keeping the output frequency of the output signal in lock step with the input frequency of the input signal.
By being able to track the input frequency, the PLL may be used to provide an output signal with a same frequency as the reference signal. In such a case, the PLL may be used for demodulation in radio or telecommunications applications. The PLL may recover information from a noisy communication channel. Alternatively, the PLL may be used to provide an output signal with a frequency that is a multiple of the input frequency. In such a case, the PLL may be used for frequency synthesis, such as providing a high frequency clock signal for synchronizing digital logic designs. Microprocessors, application specific integrated circuits (ASICs), graphics processing units (GPUs), and so forth, may utilize a PLL for generating a higher frequency clock signal from a lower frequency reference signal.
A PLL includes several components. For example, a PLL comprises a variable frequency oscillator that generates a signal with a frequency that may be in lock step with the frequency of the input signal. For a PLL on a microprocessor, the received input signal is a periodic clock signal generated off chip from a reference clock source. Using a feedback loop, a phase detector within the PLL may compare the received input signal to a divided version of the generated output signal of the PLL. In a dual-path configuration, any measured phase difference is converted into two analog voltage signals by a charge-pump and a dual-path low-pass filter. A dual-path configuration for the PLL may be used to decouple the oscillator frequency and the oscillator gain, which is directly related to the tuning range or bandwidth of the PLL. The fast control path of the PLL provides a large gain allowing a wide tuning range. The slow control path provides a small gain. The slow control path bandwidth may be several orders of magnitude lower than the fast control path bandwidth. The two analog voltage values are typically passed through a dual-path low-pass filter prior to being received by the variable frequency oscillator. These values track the measured phase difference and accordingly cause the variable frequency oscillator to speed up or slow down to allow the generated output signal to track the frequency of the received input signal.
Generally speaking, the lock time of a PLL is the amount of time it takes the PLL to move from a first specified frequency to a second specified frequency within a given frequency tolerance. The PLL lock time affects startup and frequency re-lock during operation. Time constants associated with the slow control path portion of the dual-path low-pass filter may determine and slow down the PLL lock time. A slowed lock time decreases performance.